Estimating the Inherent Parallelism in Prolog Programs

International Conference on Fifth Generation Computer Systems 1992

Pulication Type: Paper

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Abstract

In this paper we describe a system for compile time instrumentation of Prolog programs to estimate the amount of inherent parallelism. Using this information we can determine the maximum speedup obtainable through OR- and AND/OR-parallel execution. We present the results of instrumenting a number of common benchmark programs, and draw some conclusions from their execution.

Research Areas

Text Ref

D. Sehr and L.V. Kale, "Estimating the Inherent Parallelism in Prolog Programs",
Proceedings of the 1992 International Conference on Fifth Generation Computer 
Systems, Tokyo, Japan, June 1992.

BibTex

@INPROCEEDINGS{PrologParaFGCS92,
    author = "D. Sehr and L.V. Kale",
    title = "Estimating the Inherent Parallelism in {P}rolog Programs",
    booktitle = "Proceedings of the 1992 International Conference
            on Fifth Generation Computer Systems",
    year = "1992",
    month = "June",
    address = "Tokyo, Japan",
    group = Y,
}